1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device which employs a hierarchical word-decode scheme.
2. Description of the Related Art
The hierarchical word-decode scheme employs a hierarchical structure of word lines in which two types of word lines, i.e., main-word lines and sub-word lines, are used for word selection. A typical material used for word lines is polysilicon. Unfortunately, polysilicon has a relatively high resistance for a wiring material, causing a significant delay to signals propagating therethrough. A conventional technique to counter this is to establish a contact at predetermined intervals between polysilicon word lines and aluminum wiring lines arranged in parallel to the polysilicon word lines, thereby reducing a resistance of the word lines. In order to increase circuit density, however, intervals between the wiring lines needs to be shortened, but it is difficult to implement a pattern of aluminum wiring lines having the same pitch as polysilicon wiring lines. The hierarchical word-decode scheme obviates this problem by dividing polysilicon word lines into sub-word lines having tolerable delays and by using aluminum for main-word lines to achieve sufficiently small delays.
FIG. 1 is an illustrative drawing showing a word-line structure according to a related-art hierarchical word-decode scheme. A main-word decoder 201 decodes a row address to select one of main-word lines 208, and turns the selected main-word line to HIGH. The main-word lines 208 are provided on a wiring layer. In a different wiring layer, four sub-word lines 209 are laid out generally under the main-word lines 208. The sub-word lines 209 are connected to four types of sub-word decoders 204 through 207, respectively. The sub-word decoders of the same type are arranged in a row perpendicular to the extension of the main-word lines 208.
A sub-word-decoder selecting circuit 202 selects one type of sub-word decoder among the four types of the sub-word decoders 204 through 207 via the sub-word-decoder selection lines 210. The selected type of the sub-word decoders connects the main-word lines 208 to the sub-word lines 209. As a result, only one of the four sub-word lines 209 connected to the selected one of the main-word lines 208 becomes HIGH when this sub-word line 209 is selected by the sub-word-decoder selecting circuit 202. This achieves a hierarchical word selection. In the case of data-read operations, for example, data stored in memory cells (not shown) is read by sense amplifiers of sense-amplifier blocks 203 only with respect to the selected word.
The sub-word decoders 204 through 207 are provided on a wiring layer different from the wiring layer of the sub-word lines 209 laid out over the memory cells. In such a configuration, the sub-word decoders 204 through 207 are connected to the respective sub-word lines 209 via contacts 211.
It is desirable to reduce power consumption in semiconductor memory devices, and such an effort should be directed to every minute detail. To this end, sense amplifiers may be driven only with respect to a column block at a particular column address by reading the column address prior to carrying out a row-access operation. Namely, in the example of FIG. 1, only one of the sense-amplifier blocks 203 may be driven when this has an indicated column address, rather than driving all the sense-amplifier blocks 203.
In order to drive only one of the sense-amplifier blocks 203 with respect to a particular column block, a data-read operation for memory cells should be carried out only with respect to the same column block. If data is read from memory cells in all the column blocks and only one of the sense-amplifier blocks 203 is driven, some of the data is not held by the sense amplifiers since some of the sense-amplifier blocks 203 are not in operation. Such data that are not held by the sense amplifiers fail to be restored in the memory cells. As a result, data of the memory cells are destroyed in column blocks other than the column block where the sense-amplifier block 203 is operated.
In the configuration of FIG. 1, each of the sub-word lines 209 extends on either side of a corresponding one of the sub-word decoders 204 through 207, and is shared by the two column blocks on either side. If a sub-word decoder is selected only with respect to a selected column block, selection of one of the sub-word lines 209 results in data being read from the memory cells with respect to two column blocks on either side of the selected sub-word decoder. If only one of the sense-amplifier blocks 203 is driven as previously described, data destruction is bound to happen in a column block where a sense-amplifier block is not operated.
To avoid this, sub-word decoders may be provided with respect to each column block. FIG. 2 is an illustrative drawing showing another word-line structure according to the related-art hierarchical word-decode scheme.
FIG. 2 shows main-word lines and sub-word lines and relevant portions surrounding these word lines, and irrelevant portions are omitted from the figure. As shown in FIG. 2, the sub-word lines 209 extends only on one side of the sub-word decoders 204 through 207 within a span of a single column block. In this configuration, a word-selection operation can be performed only in one column block by selecting a sub-word decoder with respect to only one column block. This prevents data destruction of memory cells as previously described.
There is a reason, however, as to why the configuration of FIG. 1 is typically used instead of the configuration of FIG. 2. This issue relates to a chip size. In the configuration of FIG. 2, four contacts 211 need to be arranged in a row for each one of the main-word lines 208. The contacts 211, however, cannot be arranged so close to each other. Intervals between the sub-word lines 209 are thus bound to be wider in the configuration of FIG. 2 than in the configuration of FIG. 1, resulting in a chip size being increased in a vertical direction of the figure.
Further, the configuration of FIG. 2 has a complete set of sub-word decoders for each column block. This means double the number of sub-word decoders compared to the configuration of FIG. 1. Chip size in a horizontal direction of the figure is also enlarged.
Accordingly, there is a need for a semiconductor memory device in which a complete set of sub-word decoders is provided for each column block without enlarging a chip size.